Morse-to-binary code translator



July 20, 1965 B. MURRAY 3,196,210

' MORSE-TO-BINARY CODE TRANSLATOR Original Filed Nov. 12, 1959 8lSlfxeeiss-Sheet 1 Manx-1 a A I l 05ml, o it a F; o 4*: o

ATTORNEY July 20, 1965 B. MURRAY MORSE-TO-BINARY CODE TRANSLATOROriginal Filed Nov. 12, 1959 8 Sheets-Sheet 2 KWWWQ ..53 HTJI wwtINVENTOR.

@muy Mu/@Hy BY f2? C /JWJ .TTRNEY July 20, 1965 B. MURRAY 3,196,210 4MORSE-TO-BINARY GODE TRANSLATOR Original Filed Nov. 12, 1959 8Sheets-Sheet 3 P S 0 l O START i SPAC COUNTER D5 D4 la ,5, a gz 0.6.6. YA 6 a 1 l a H l o I" o "fl o n "A A l A f4 bra IN V EN TOR.

ATZWRMEY July 20, 1965 4 B. MURRAY 3,196,210

MORSE-TO-BINARY CODE TRANSLATOR Original Filed Nov. 12, 1959 8Sheets-Smet 4 ATIURNEY July 20, B. MURRAY I MORSE-TO-BINARY CODETRANSLATOR Original Filed Nov. 12. 1959 8 Sheets-Sheet 5 Il l Fzlg: 8

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ATTORNEY July 20, 1965 B. MURRAY MORSE-TO-BINARY GODE TRANSLATORoriginal Filed Nov. 12, 1959 8 Sheets-Sheet 6 July 20 1965 a. MURRAY3,196,210

MoRsE-To-BINARY GODE TRANsLAToR Original Filed Nov. 12, 1959 8Sheets-Sheet '7 CORS FRI' QUENC Y CONI fvg/0 INVENT BY @CW ATTORNEY 8Sheets-Sheet 8 I Original Filed Nov. 12, 1959 f PULSES INVENTOR.

www 1l/@Ray BY ,4% C #W4 ATTORNEY United States Patent, O

3,1%,Zitl MRSE-T-BENARY @GDE TRANSLATGR Eiradiey Murray, GeorgetownPreparatory Sehooi, Garrett Park, Md.

@riginal application Nov. l2, i959, Ser. No. $52,547, new Patent No.3,ii38,ti3ti, dated .lune 5, 11%2. Divided and this application Nov. 30,196i, Ser. No. 156,053

6 iliaims. (Ci. 17d-26) This application is a divisional of my copendingapplication Serial No. 852,547, filed November l2, 1959, now U.S. PatentNo. 3,038,030, issued lune 5, 1962, for Morse-To-Binary Code Translator.

rIhis invention relates to a Morse code translator, and moreparticularly to code speed detection circuits for the Iriorse-to-binarycode translator.

The invention described and claimed in the copending application isdirected to the translator, per se, utilizing standard digital computercomponents. In this application novel code speed detection circuits areclaimed which have particular utility with my code translator describedin the copending application.

Accordingly, it is a primary object of this invention to provide, incombination, a translator for converting Morse-to-binary code, utilizingdigital techniques and code speed detection circuits for maintaining theaccuracy orn the translator.

It is another object of the invention to provide code speed detectioncircuits having both tine and coarse control over the number of pulsesgenerated for indicating dots and dashes.

In accordance with an aspect of the invention, there is provided, incombination, a Morse code to binary code converter comprising a pulsegenerator for generating start and finish pulses identifying,respectively, the beginning and end of a Morse character. A signalelement counter is coupled to the generator and is adapted to produce agiven number of pulses in response to start and finish pulses indicativeof a dot and a different number of pulses in response to start andfinish pulses indicative of a dash A code speed detection circuit iscoupled to the output of the signal element counter for determiningwhether the number of pulses generated thereby correspond to the givennumber. If the generated pulses do not correspond to the given number,means are provided to increase or decrease the frequency of generatedpulses until correspondence is achieved.

The above-mentioned and other features and objects of this invention andthe manner of attaining them will become more apparent and the inventionitself will be v best understood by reference to the followingdescription of an embodiment of the invention taken in conjunction withthe accompanying drawing, wherein:

FIGURES lA-lD .and 2 are diagrammatic illustrations of logic blocksemployed in the invention;

FGURES 3A and 3B are schematic diagrams of two forms of a line counter;

FIGURES 4A and 4B are schematic diagrams of two forms of space counter;

FIG. 5 is a schematic diagram of a Morse-to-pulse counter;

EGUEE 6 is a simplied diagram of a sequence determining circuit used inthe Morse-to-binary converter;

FIGURE 7 is a schematic diagram of the second stage of theMorse-to-binary code converter;

FIGURE 8 is a schematic diagram similar to FiGURE 7 and including memorycircuits for providing a partial memory oi the binary code;

EGURE 9 is a schematic diagram of a code speed detection circuit;

ICC

FIGURE l0 is similar to FIGURE 9, including circuitry for increasing therange of speed detection; and

FIGURE 11 is a chart showing the condition of each flip-flop in thespace counter of FIGURE 3A during the application of fifteen successiveinput pulses.

In order that the description of the invention may be clearlyunderstood, a brief description of the basic building blocks of thedecoder wili first be given.

Referring now to FIG. l, the four fundamental building blocks arediagrammatically illustrated, which diagrams shall be used throughoutthe other gures. These circuits are: the dip-iop (FIG. 1A), theunivibrator (oneshot) or monostable trigger (FIG. 1B), the logic ANDgate, and the logic OR gate.

The flip-flop (FIG. 1A) has three inputs: the reset input (A), whichresets the dip-flop to the oit, or 0, state; the set input (E), whichsets the tlip-iiop to the on, or 1, state; and the complementary(binary) input (C), which causes the fiip-iiop to change state onsuccessive pulses. There .are four outputs, two of which producesteadystate signals, and two of which produce pulses, as indicated bythe capacitors. The two outputs marked a are the 0 outputs, producingrespectively an output pulse when the dip-flop changes from 1 to 0, anda steady-state, gate-enabling signal when the ilip-fiop is in the Ostate. The opposite obtains for the leads marked b. The univibrator(FIG. 1B), represented by a square marked U-V, has a single input andsingle output. It is used for pulse-delay purposes.

The AND and OR gates (FIGS. 1C, 1D) are represented by rectangles of anyconvenient size, with inputs represented by iii-going arrows, outputs byout-going arrows. No distinction is made between active andpassivevgates, since such a distinction has no bearing on the generalcircuit description.

M orse-o-pzrlse converter The iirst stage of the decoder converts theMorse signal into groups or" pulses suitable for the counting circuitsto foilow. in order to define more sharply the start and iinish of anyMorse character, the characters are made to generate start and nishpulses by the circuit of FEGURE 2. The Morse characters are fed into anamplifier biased to cutoff (or, if advisable, into an amplifieroperating at saturation). The output of the amplitier is differentiatedby a standard R-C circuit, so that the start of a Morse character willgenerate negative-going signals, and the end ot a characterpositive-going signals, or vice versa. The negative pulses areamplified, and the positive pulses are ampiied and inverted for use inthe decoding circuits. rEhe diodes separate the two kinds of pulses.

The Morse characters are converted into pulses by using the start andinish pulses to gate an oscillator or pulse generator.

If the code characters are used to gate a generator, the number ofpulses generated for a long and short will be in the ratio of 3:1, sincethis is the time-duration ratio of the ideal Morse code. A 3:1 pulseratio would, however, introduce complexity in the second stage, wherethe pulses are converted into a binary code. For minimum complexity,therefore, the pulses are generated having a 2:1 ratio.

The line or signal element c0zmter.-The term line is used to designatethe presence of a Morse character; the term space to designate itsabsence, as in the spaces between characters of a letter, betweenletters, and between words. l i

FIGURES 3A and 3B show two counters designed to give a single outputpulse for a dot, and two output pulses for a dash. Each counter allowsthe Morse character to deviate from the ideal length of a dot or dash.

In FIGURE 3A, four dip-Hops i, 2, S and i are con- =be generated by thenected conventional binary counter. An input AND gate is conditioned bythe Morse characters (i.e., by the start and iinish pulses describedabove). An oscillator is adjusted to a frequency lor pulse repetitionrate such that the dot of ideal length will gate lthree pulses into thecounter, and a dash of ideal length nine pulses. The output fromflip-dop 1 is connected over a blead to an AND circuit d having threeinput leads; an output pulse, therefore, is applied to the gate on inputpulses 1, 3, 5, 7, 9, 1l, 13, 15. In FIGURE 11 the applied pulses andtheir effect on the tlip-ilops are charted for ease in fol- -erated by adot produces an output pulse, a dot can be about 33 percent shorter thanthe ideal. It is recalled that a dot is indicated by one pulse. Adnd,since a second output pulse is not generated until the 5th input pulse,the dot can be about 33 rpercent longer than the ideal. The ideal dashwill generate 9 input pulses. In this counter, the dash can be shortenough to produce only 5 (giving the second output pulse, indicating adash is being received), and long enough to generate input pulses(beyond 15 the cycle is repeated, and 3 output pulses would begenerated, causing error).

The clearing or resetting of the counter does not produce a false outputpulse, for there can be no output unless the Iirst flip-iiop ll changesfrom "0 to 1. If the iirst hip-flop is in the 0 state when the resetpulse is applied, it does not change state, and no pulse will appearacross the capacitor.y And, if it is in the 1 state, the reset pulsechanges it to 0.

The counter of FIGURE 3B is an improved embodif ment especially as toallowable deviation from the ideal code. The four ilip-ops 7, 8, 9 and10 of this counter are interconnected differently from the counter ofFIG- URE 3A. The connections as indicated rnalre the counter ascale-of-ve, that is, the fifth input pulse produces an output pulse.The method of obtaining various scaling ratios is known and is describedin an article entitled A Variable Binary Scaler, LRE. Transactions onElec tronic Computers, vol. EC-4, No. 2 (June 1955), pp. 70-74, writtenby Bradley Murray. This counter is diiercnt from the counter or FIGURE3A in two important respects: the inclusion of univibrator I1 and thebinary flip-ildp stage 10.

The univibratorplll is employed to delay the start l pulse, since thisstart pulse is also used to clear certain sections of a second part ofthe decoder. The delay time of the univibrator should be adjusted toabout the same duration as the'tirne betwen pulses of the oscillatorwhen it is operating at its maximum frequency. The reason for this isexplained below.

The purpose of the fourth binary stage 10 is clear from an examinationof the operating sequence of the scale-of- IiVe counter: 0000, 1110,0110, 1010, 0010, 1101, 0101, 1001,'0001, 1111, 0111, 1011, 0011, 1100,0100, 1000, 0000. An output pulse is generated on the a lead of thethird ilip-tlop 9 when it changes from state 1 to state 0. This changetakes place on the 5th and 9th input pulses. Thus, if the duration otradash were even slightly greater than the ideal, three output pulses,instead of two, would line counter through the OR circuit indicated: oneby the start pulse, and two by the scaleoi-ive counter. By taking theoutput from the b lead of flip-flop 10, however, an output pulse isobtained from the OR circuit only on the 1st, 5th and 21st inputpulses-that is, the delayed start pulse, and when the Vdeviation of adash from the ideal. The lowerlimit is the same as for the irst counterdescribed. The lower limit of a dot is practically unlimited, since itneed be long enoughV only to generate a short pulse, which, in currentcomputer design, is less than a microsecond. The upper limit of a dot isthe saine as for the first circuit lescribcd.

The space commen-It is necessary to distinguish between three differentkinds of spaces: the short space, equal in duration to one dot, and usedto indicate the space between characters of a letter; the longer space,equal( in duration to three dots, or a dash, and used to indicate thespace between letters; and the long space, equal in duration to six dotsor two dashes, and used to indicate the space between words. Y The twocounters for distinguishing spaces are shown in FISI RES 4A and 4B.These counters are basically the same as those used for the linecounter. In FIG- URE 4A, the pulses from first dip-flop 12 are gated bythe second and third flip-tops 13, 14, so connected that only the 5thand 13th input pulses generate eective output pulses. A pulse generatedby a short space is not required, since a iinish pulse can supply itsfunctions. The ideal-length letter space will gate 9 input pulses to thecounter, and the 5th of these produces an output pulse. The ideal-lengthword space will gate in 18 pulses, and the 13th of these produces thesecond output pulse. When the rst output pulse is passed by the ANDcircuit 15, it sets the print ilip-tiop l to its 1 state. This ilipflophas a number of functions besides producing a letterprintingv signal.The only one to be noted here is that it conditions `an AND gate 16. Theiirst output pulse cannot pass through this gate, since the fprinttiipdiop P is initially in its 0 state, before the arrival of the rstpulse. That is, the pulse applied directly to the AND gate lo isterminated before the output from l is applied to the gate 16, Wherepulses are of relatively long duration, it would be necessary to insertsome kind of delay unit, of about one-pulse duration, in the lower inputlead to the AND `gate 16.

The second output pulse, indicating a long wordspace space, has noeffect on the ip-tlop P (since it is already in the l state from theprevious pulse), but is passed to the space `flip-flop S through the ANDcircuit 16, thereby changing the dip-flop S to the l state. Subsequentpulses will have no effect on'either of these flip-flops, until they arereset. The space dip-flop S is used to actuate the space-bar mechanismon the typewriter or printer. Both of these dip-deps are reset (on thelead marked R) by the same reset pulse. This is possible because manytypewriters ywill insert a space after a letter, even if the space-baris depressed whilethe letter key is held down.

In FIGURE 4B the same kind of sealer is employed as in FIGURE 3B.Actually this is a scale-o-five or a scale-cf-thirteen, depending uponwhich output lead of the fourth tlip-iop is used. The b lead generatesan output pulse on the 5th input pulse, and the cz lead generates one onthe 13th. The b lead sets the print dip-flop P, and the a lead sets thespace flip-oprS.

When the set andreset inputs 4of a ilip-op are used, they can usually bereset by `a pulse of the wrong polarity on the set input; and set by awrong pulse on the reset input. This cannot happen in the circuit ofFIGURE 4A, if the AND gates 15, 15 pass pulses of only the correct(negative) polarity; and, therefore, diodes D1 and D2 in the FIGURE 4Awould be superuous. Diodes D3 and D4, however, are needed in the circuitof FIG- URE 4B.V Y

Combined M orse-io-pulse c0nverter.-FIGURE 5 cornbines the line andspace counters of FIGURES 3B and 4B just described. The following is adescription of the operating sequence:

When a Morse character is received, a start pulse is generated. Thispulse sets a pulse generator capable of producing a pulse of variableduration, e.g., control flipop `C =t 1, resets P `and S to 0; fandgenerates an output pulse in the line counter through U-V 11. As Cchanges state from 0 to 1, it generates a pulse on the 1b lead to resetthe space counter, and, at the same Morse characters to be decoded(except for punctuation marks). The maximum number of characters in aletter is 4. Of the 4-groups there are four possible codes not useddash-dash-dash-dot (22), the dot-dash-dot-dash (25), dot-dot-dash-dash(27), and dash-daslrdash-dash time, generates a steady-state signal tocondition the in- (30). These could well be used for special symbols andput gate 17 to the line counter. If the character being instructions.Among the tive-and six charater codes (nureceived is a dot, no pulse isgenerated from the hip-flops merals and punctuation), there are many notused, but or" the line counter, and, therefore, only a single pulsethese lack the brevity ofthe ones mentioned.

(the output from U-V) is passed to the next stage. If For numerals, theMorse code uses a tive-character the character is a dash, an additionalpulse is generated, code; and, therefore, six binary stages are needed.For and two pulses pass to the next stage. At the completionpunctuation, which uses a six-character code, an excepof the Morsecharacter, a finish pulse is generated, which tion is made to thegeneral rule. The sixth Morse charresets C from 1 to 0. This generates apulse which clears acter, instead of being fed into the sixth stage, isfed back the line counter over line a, and a steady-state signal intothe first stage, and the resulting binary code is still which conditionsthe input gate 18 to the space counter. different from that of any otherletter or numeral. If the space is short (one dot) there is no outputfrom the IGURE 7 shows a practical circuit for this pulse-tospacecounter. If it is longer (one dash) or long (tv/o binary counter. The ORoutput gate of the line counter cla-shes) one -or two pulses aregenerated t0 set either P, of FIGURE 5 has been redrawn as indicated.The outor P and S, as described above. The next Morse characput pulsesfrom the OR gate are fed simultaneously t0 ter repeats this cycle. sixAND gates 25, 26, 2.7, ZS, 29 and 30. These gates y are controlled by athree-stage binary counter 31, 32, PulseO-bmary converter 33. When thethree-stage counter is at 000, the rst AND The second stage of thedecoder converts the pulses gate is enabled; when it is at 100, thesecond gate 26 and pulse pairs of the iirst stage into a binary code. 25is enabled, and so forth. (The numbers on the AND Obviously it is notenough simply to count these pulses, gate input leads correspond tothose on the steady-state since the number of pulses generated bydifferent letters output leads of the three-stage counter.) In this way,the may be the same. Consider, for instance, D (dash-dotoutput pulsesfrom the line counter are fed to the dot), R (dot-dash-dot), and U(dot-dot-dash). Each proper leads for input to a six-stage binarycounter 34, of these letters consists of one dash and two dots-a 35, 36,37, 38 and 39 shown at the top of the figure. total of four pulses. Notethat the output from the sixth AND gate 30 is fed FIGURE 6 shows asimplied arrangement by which to the input of the iirst stage 34 of thecounter. the order ot appearance of the dots and dashes can be Thesequence of operation is as follows. When the distinguished. The rstMorse character of a letter is print ip-ilop, P, from the previous stage(FIGURE 5) fed to the input of the iirst -ip-op Ztl, the second to theis reset by a start pulse, it generates a pulse which resecond flip-flop21, the third to the third tlip-op 22. sets both the three-stage and thesix-stage counters. The The diodes 23, 24 prevent the input pulses tothe second start pulse itself cannot be used for this clearing funclandthird Hip-flops from effecting the preceding stage. tion, or it wouldreset the counters after each Morse char- In the case of the letter D,two pulses (dash) are fed acter, instead of after each complete letter,as required. into the first flip-flop, one pulse (dot) into the second,The P ilip-op, however, is not reset until the rst start and one pulse(dot) into the third. The state of the pulse after a completed letter.counter after each Morse character will be: 0100, 0010, When the rstMorse character of a letter is received, 0001, the tinal state being thebinary representation of it generates one or two pulses from the linecounter, decimal 8. The sequence of operation for the letter R dependingupon whether it is a dot or a dash. Since the is; 1000, 1010, 1001, thenaal state being the binary three-stage binary counter has been reset to000. only equivalent of decimal 9. The sequence for U is 1000, the irststage 25 of the six-stage binary counter is re- 1100, 1101, the finalstate being decimal 11. sponsive to this pulse or pair of pulses. Whenthe char- Extending the counter to six stages, there will be a acterends, a finish PUIS@ iS generated, which advances unique binaryequivalent for every letter, numeral, and r the three-stage counter tothe next binary number, 100, punctuation mark, as shown in the followingtable. "9 thereby conditionmg the second AND gate 26, and per- MorseBinary Dec Morse Binary Dec.

E 100000 1 Free 100110 25 '1 010000 2 010110 20 I 110000 3 Free 11011027 N 001000 4 Y 001110 2s A 101000 5 J 101110 29 M 011000 6 Free 01111030 S 111000 7 5 111110 31 D 000100 s 000001 32 R 100100 0 010001 34 G010100 10 011001 as U 110100 11 011101 40 K 001100 12 111101 47 w 10110013 111011 55 o 011100 14 110111 59 H 111100 15 101111 01 B 000010 16011111 02 L 100010 17 111001 39 Z 010010 1s 100101 41 F 110010 19 01010142 C 001010 20 001100 44 P 101010 21 001011 52 Free 011010 22 101011 53V 111010 23 000011 4s X 000110 24 010011 50 As a general rule, thenumber of stages required in this type of counter will be one more thanthe number of mitting the next pulse or pair of pulses to be feddirectly int-0 the second stage 35 of the six-stage counter. This cycleis repeated until the space counter of FGURE 5 detects a long space(whether it is a letter-space orY a word-space). Flip-flop P is thenchanged from to 1. The next start puise resets P, clears both counters,and the process is repeated for the next group of characters.

1t was mentioned above in connection with the univibrator of FGURES 3and 5, that the delay time should be adjusted to about the same durationas the time between pulses of the oscillator when it is operating at itsmaximum frequency. The reason for this can be understood from FlGURE 7and the preceding description of its operating cycle. 1f there is nodelay time, the start puise which indicates a dot would be fed to thecircuits or FEGURE 7 before the same start pulse had time to clear them.On the other hand, this delay cannot be too long, for the three-stagecounter of li'f- URE 7 is advanced by each finish pulse, and, if theduration ot a dot were very short, the nish pulse might advance thethreestage counter before the arrival ot the dot pulse, thereby causingthe dot pulse to be fed into the wrong stage. y

Partial memory The operating time of the decoder isV limited only by thecomputer components, and these have been designed to operate at speedswell over a megacycle. Therefore, the only practical limitation onreceiving speed is imposed by the printing mechanism. 1n the decoder, asdescribed thus far, the time allowed for printing extends from the thpulse gated into the space counter to the start puise of the followingMorse character. If the spaces are of ideal duration (gating 9 pulsesfor a letter-space and 18 for a word-space), Vthis would be equivalentto a printing time of about one and one-third dots for a letterspace-andit is this shorter letter-space which determines the maximum receivingspeed. If the spacing is not of ideal duration, the printing time can beas short as onetnird ot a dot. To overcome this speed limitation-thatis, to increase the printing time by distributing it among the letterswith more than two characters, standard memory circuits can beincorporated in the decoder. These memories would be written into at theconclusion of each letter, and read out at periodic intervals,corresponding to the speed at which the code is being received. Suchmemories give the printing mechanism time to catch up, whileV letters ofmore characters are being decoded. These memories, however, are not partof the invention and, therefore, are not described in det-ail.

With a slight change in circuitry it is possible to incorporate apartial memory, which gives an increase in the printing time, and,therefore, a corresponding increase in thek speed capability of thedecoder. This memory has been designed around the shortest of the Morseletters, E, which consists of a single dot. The worst possible case, theshortest printing time for a letter, is had when the letter E isfollowed by another E. However, by terminating the printing time withthe finish pulse of the E, instead of with the start pulse the printingtime can be extended for the `duration of the E-one dot, for an idealcode.

FIGURE 8 shows the circuit of this partial memory. It is basically thesame as FIGURE 7, except for the addition of M1 and M2, the partialmemory nip-flops.

vThese two tlip- Lops control the resetting of the first two stages 3d,35 of the six-stage binary counter; and this counter is reset on afinish pulse to P, rather thanon a start pulse as in FIGURE 7.

The operating cycle is as follows. The pulse or pulse pair (dot or dashpulses) are fed from the line counter over AND gate 25 to the memorypair, M1-M2-setting this pair to either 10 for a single-pulse dot, or 01for a double-pulse dash. At the termination of the iirst Morsecharacter, a finish pulse is generated. This pulse advances thethree-stage counter (not shown) just as it did in P IGURE 7. 1t alsoresets P from 1 to 0. As P resets, it generates pulse on its a lead,which is' fed directly to the stages 36, 37, 38 and 39, of the counter,resetting them. The same yresetting pulse is fed to the two pairs ot ANDgates 40, 41. controlled by the Mil-M2 pair. Thus, the iirst -two stagesof the six-stage counter are reset to the same state (l0, or 01) as thepartial memory pair. The second, third, etc. Morse characters are ted tothe stages 3d, etc. as they were in FiGURE The sixth Morse character(punctuation), however, is not fed to the partial memory input, as wasthe tirst characier, but back into the iirst stage of the six-stagecounter.

At the end of a completed letter, the fifth pulse into the space countergenerates the pulse that sets P from 0 to 1. in so changing, P generatesa pulse on its b lead, which resets both the partial memory pair, andthe three-stage binary counter, preparing them for reception of theiirst Morse character of the next letter. Both the memory pair and thethreestage counter can be reset at this time, since they are not neededfor the printing operation which begins as i changes from 0 to l.

Code speed detection As mentioned previously, the invention claimed inthis application is directed to code speed detection.

The determination of code speeds, and the consequent adjustment of theoscillator frequency is also designed around digital components. 1t is,however, partially adaptable to analogue techniques.

Adjustment of the oscillator is divided into two functions: linefrequency adjustment and coarse frequency adjustment.

'Fine frequency adjustment- A dash is used as the standard ofmeasurement, since there is no difficulty about the shortness of adotthe start pulse is suicicnt to indicate its presence. Presuming thecoarse frequency has been so adjusted that a dash will generate 5 to 12pulses in the line counter, the oscillator is regulated so that nine(the ideal number) pulses are generated in the counter. The detectoruses a finish pulse to read the condition of the line counter, and tomake the required correction. There follows a chart of the operatingsequence of the line counter, which, it will be remembered, is ascale-of-iive counter:

Coarse Frequency Fine Frequency Coarse Frequency Increase Control YDecrease 0-.- 00000 Inc.x3 5 11010 0 13-- 11001 Dec.x2

14.. 01001 Dee.x2 1--- 11100 0 6 01010 Inc. 1 15-. 10001 X2 10.. 00001x2 2 01100 0 7 10010 Inc. 1

' 17 11101 X3 3- 10100 0 8--. 00010 1110.1 18-- 01101 X3 19- 10101 i34--- 00100 0 9--- 11110 0 20-- 00101 )i3 2L- 11011 i3 10.. 01110 Dec.122-- 01011 x3 23-- 10011 x3 11., 10110 1300.1 24 00011 X3 25-- 11111 X312.. 00110 Dec.1 25.. 01111 x3 27 10111 x3 28 00111 x3 The center columnor the chart deals with the pulses (5-12) which concern tine frequencycontrol. First is listed the pulse number, then the condition' of theline counter' after the pulse is received, and finally the correctronthat is to be made. It should be noted Ithat for pulse 5, no change ismade. This is because the iifth pulse might be generated by a dot thatis too long. If it' is actually a dash generating only tive pulses, thenthe condition will be corected by the coarse frequency con-a trol. Allthe other corrections consist in Varying the frequency of the oscillatorto give only one more (or less) pulse for the same length codecharacter. Thus, all changes in the tine frequency control aremadegradu-ally; and a single character which is too long or too shortwill not cause a large deviation from the average length.

rThe upper part of FIGURE 9 (above the dotted line) shows the circuitswhich fulfill the requirements for ne frequency control. The flip-flopsat the bottom '7, 8, 9 and lil for the binary notations l, 2, 4 and 8are the same ones as shown in the line counter of FIGURES 3 and 5; andthe univibrator 1l of FIGURE 5 is shown at the bottom of FIGURE 9. Anadditional flip-flop 45 for the binary 16 has been added for purposes ofcoarse frequency control. According to the chart, an increase of l pulseis required for the condition when nipllop 1t) is on (output on 8b),flip-flop 9 is olif (da), and either flip-flop '7 or flip-flop S, orboth, are oif (tml-2a). Under these conditions, a linish pulse F willpass through the gate 4.3:

Incr. 1:(F) (1mi-2a) (4a) (Sb) The conditions for a decrease of l pulseare met by: Deer. 1=(F) (la-i-Zrz) (lb)(8b) lf it should be desired tomake a correction when the line counter reads 5, then the line from theOR gate lo la-l-Za) should be disconnected from the Increase 1 circuit48.

After a finish pulse passes through one of these two gates 42,' 43, itenergizes a univibrator 47 or 43 in the output of which is, for example,a stepping relay 49 or i), connected to a potentiometer (not shown). Thepotentiometer controls the frequency of the oscillator. The univibratoris adjusted to change the frequency by approximately one pulse. Thisadjustment will vary, of course, according to the setting of the coarsefrequency control. If a given change of resistance causes a certainchange in frequency when the oscillator operates at 5i) pps., the samechange in resistance will cause a different change in frequency when theoscillator operates at 300 pps. Because of the relatively narrowfrequency range of the oscillator in this application, these differencesshould not be important.

The coils of stepping relays 49, Sti are shown in FIG- URE 9. Forincreasing and decreasing, the Steppers could feed into a computingdifferential gear, and the output of the gear into a potentiometershaft. Or, the coils could actuate cip/dt relays which change thepolarity of a small D.C. motor, as used to drive potentiometers inanalogue circuits.

Since the finish pulse reads the state of the line counter, it isimportant that this counter is not cleared before the nish pulse canread it. Resetting of the line counter' is accomplished (FIGURE 5)indirectly by the finish pulse, through control ilip-llop C. If thefinish pulse is short, compared to the switching time of the controlflip-nop, no ditiiculty will be encountered. If it is not, there is needfor a delay 51 in the reset lead of the line counter as suggested bydotted lines, equal to a bit less than one pulse, when the oscillator isoperating at its maximum frequency.

Some measure of control can be exercised over the space counter byincluding a similar tine frequency control. The coarse frequency controlof the space counter would be handled by the coarse frequency control ofthe line counter. If this is done, a separate oscillator would be usedfor the space counter.

Coarse frequency c0ntrol.-"Ihis is accomplished by double, tripling,etc. the oscillator frequency, according to the requirements of theabove chart. The only increase (tripling, as indicated by x3) is madewhen the line counter shows all flip-flops in the O-state. All othercircuit conditions are indicated on the output leads to the Variousgates of FIGURE 9. The univibrators are adjusted to stay on forcorrespondingly longer periods, allowing a motor or self-stepping relayto accomplish the required changes. Where the code is being receivedvery rapidly, the full change may not be accomplished before the nextseries of pulses comes into the line counter, but this is of noconsequence.

The circuits of FIGURE 9 give a fairly limited range of receiving speeds(about 3-to-1). They are shown mainly for purposes of illustrations. Inorder to increase the range, additional flip-flops and gates are added.FIG- URE 10 illustrates this. With the addition of one more nip-nop, forthe binary notation 32, the range can be increased to about 7-to-1. Thecomplementary output of each additional lip-llop must be added to thegate to Increase x3, since this is done only when the entire counter isat 0.

It is not necessary to make similar provisions for the gates to Decrease2, Decrease 3, etc., because all of these univibrators are parallelsupplies for the relay coils; and, in the case of overlapping (i.e.,when two are turned on at the same time) the one with the longer periodwill prevail.

Variation- A method more closely allied to analogue methods can be usedfor the coarse frequency control. Instead of reading the line counter, aseparate counter may be added to the decoder (and this counter may bestraight binary code). Pulses to the line counter are also fed to thiscoarse frequency control counter. The motor which operates theresistance (potentiometer) in the oscillator also operates ananalogue-to-digital converter. The motor is energized during the spacesbetween code characters and the analogue-to-digital converter is sowired that it seeks the binary code for 9 pulsesthat is, the motor isnot energized when the counter reads 9. Like the coarse frequencycontrol just described, the motor increases the frequency only for thecondition when all hip-flops of the counter read 0. If the linefrequency control described above is included, the motor would also bede-energized for pulses 1 through 12, with the line frequency controltaking over for pulses 5 through l2. If the line frequency is not used,it is still necessary that the motor be fle-energized for pulses 1, 2, 3and 4, since these pertain to a dot; and the control of frequency iscentered around the length of a dash.

Printing No specilic printer is designed for the novel decoder; and,consequently no network is included to convert the binary code to aspecic letter on the printer. The network will depend on the printerused; and, in any event, it would consist of a standard diode network,or the equivalent.

With the advent of high-speed, dry-ink printers, there is no practicalupper limit to receiving speeds. Where mechanical printers are used,certain requirements must be observed.

If a full memory is not used, there will be difficulty in shifting thecarriage to a new line, since certain letters will be lost, during theprocess. Therefore, a printer with a tape (not requiring carriagereturn) would be required. If however, the sender is sending codespecifically to this receiving device, one of the spare charactersmentioned in the table could be sent to indicate carriage return. Twoothers could be used to indicate a shift to upper case and a return tolower case.

If the printer is of a type which does not insert a space, while aletter key is depressed, some modification must be made in flip-flop Pand llip-ilop S of FIGURES l and 5, so that P is reset before S.Example, S could be used to reset P.

While the foregoing description sets forth the principles of theinvention in connection with specific apparatus, it is to be clearlyunderstood that this description is made only by way of example and notas a limitation of the scope of the invention as set forth in theobjects thereof and in the accompanying claims.

I claim:

l. In a Morse code-to-binary code converter,

a first pulse generating means for generating start and linish pulsesidentifying respectively the beginning and end of a Morse signalelement,

l. l a second kpulse generating means having a predetermined pulserepetition rate of higher frequency than the frequency of said start andfinish pulses, gating means coupled to the output of said irst andsecond generating means for passing pulses from said second generatingmeans during the period between said start and finish pulses,

, whereby said gating means passes a given number of pulses indicativeof a dot and a diiferent given number of pulses indicative of a dash,

a binary multistage signal element counter means coupled to the outputof said gating means, whereby the condition of each stage is dependentupon the number of pulses applied to said counter means,

detecting means coupled to the output of said first pulse generator andto predetermined stages of said counter means for detecting thecondition thereof upon the occurrence of a nish pulse,

whereby the condition of the detected stages is related to the pulserepetition rate of said second pulse generator,

and frequency correction means coupled to said second pulse generatorand to the output of said condition detecting means for increasing ordecreasing the pulse repetition rate of Said second pulse generator ifthe condition of said stages indicates a deviation from saidpredetermined pulse repetition rate.

2. In a Morse code-to-binary code converter as defined in claim 1, inwhich said detecting means includes a plurality of circuit means,

each circuit means being coupled to a predetermined number of saidstages,

each circuit means producing a control signal depending upon thecondition of the predetermined number of said stages said frequencycorrection means being responsive to the control signal produced by anyof said circuit means.

3. In a Morse code-to-binary code converter as defined in claim l, inwhich said detecting means includes a irst plurality of circuitmeans,

each of said circuit means being coupled to a predetermined number ofstages,

one of said circuit means producing a control signal when the conditionof the predetermined stages to which it is coupled is that the pulserepetition rate is below the desired rate,

a second plurality of circuit means,

each of said second plurality of circuit means being coupled to apredetermined number of stages,

one of said second circuit means producing a control signal when thecondition of the predetermined stage to which it is coupled is that thepulse repetition rate is below the desired rate,

and said frequency correction means being responsive to the controlsignal produced by said rst plurality of circuit means or said secondplurality of circuit means.

4. In a Morse code-to-binary code converter as deiined in claim in whichsaid detecting means includes a third circuit means coupled to each ofsaid stages to determine the presence of any pulses,

said third circuit means producing a control signal when stages readzero,

and said frequency correction means producing a large l2 correction inresponse to said control signal from said third circuit means.

5. ln a Morse code-to-binary code converter as deiined in claim l, inwhich said detecting means includes a plurality of AND circuits,

ysaid first pulse generator being connected as an input to each ANDcircuit said stages of said counter being coupled in predeterminedgroupings as inputs to predetermined AND circuits, whereby one of saidAND circuits will produce an output control signal if the number ofpulses counted by said stages are not equal to the predetermined pulserepetition rate of said second pulse generating means,

and said frequency correction means includes a plurality of correctionpulse producing means coupled to said AND circuits respectively andresponsive to an output control signal and relay control meansresponsive to said correction pulse producing means for increasing ordecreasing said pulse repetition rate.

6. In a Morse code-to-binary code converter,

a first pulse generating means for generating start and nish pulsesidentifying respectively the beginning and end of a Morse signal elementa second pulse generator means having a predetermined pulse repetitionrate of higher frequency than said start and iinish means gating meansincluding AND circuit means coupled to the output of said iirst andsecond generating means for passing pulses from said second generatingmeans during the period between said start and linish puises,`

whereby said gating means passes a given number of pulses indicative ofa dot and a diiierent number of pulses indicative of a dash binarymultistage signal element counter means coupled to the output of saidgating means, whereby the condition of each stage is dependent upon thenumber of pulses applied to said counter means detecting means coupledto the output of said iirst pulse generator and to predetermined stagesof said counter means for detecting the condition thereof upon theoccurrence of a finish pulse including a` plurality of AND circuits andmeans selectively coupling said AND circuits respectively to apredetermined plurality of said stages whereby the condition of thedetected stages and said AND circuits are related to the pulserepetition rate of said second pulse generator,V

Y and frequency correction means coupled to and responsive to saiddetecting means for increasing or decreasing the pulse repetition rateof said second pulse generator if the condition of said stages indicatesa deviation from said predetermined pulse repetition rate.

References Cited by the Examiner UNITED STATES PATENTS 2,919,854 1/60Singrnan 340-146.1 XR 2,945,221 7/60 Hinton et al. 178-26 XR 3,038,0306/62 Murray 17g-26.5

NEU. C. READ, Primary Examiner.

MALCOLM A. MORRTSON, ROBERT H. ROSE,

1 Examiners.

1. IN A MORSE CODE-TO-BINARY CODE CONVERTER, A FIRST PULSE GENERATINGMEANS FOR GENERATING START AND FINISH PULSES INDENTIFYING RESPECTIVELYTHE BEGINNING AND END OF A MORSE SIGNAL ELEMENT, A SECOND PULSEGENERATING MEANS HAVING A PREDETERMINED PULSES REPETITION RATE OF HIGHERFREQUENCY THAN THE FREQUENCY OF SAID START AND FINISH PULSES, GATINGMEANS COUPLED TO THE OUTPUT OF SAID FIRST AND SECOND GENERATING MEANSFOR PASSING PULSES FROM SAID SECOND GENERATING MEANS DURING THE PERIODBETWEEN SAID START AND FINISH PULSES, WHEREBY SAID GATING MEANS PASSES AGIVEN NUMBER OF PULSES INDICATIVE OF A DOT AND A DIFFERENT GIVEN NUMBEROF PULSES INDICATIVE OF A DASH, A BINARY MULTISTAGE SIGNAL ELEMENTCOUNTER MEANS COUPLED TO THE OUTPUT OF SAID GATING MEANS, WHEREBY THECONDITION OF EACH STAGE IS DEPENDENT UPON THE NUMBER OF PULSES APPLIEDTO SAID COUNTER MEANS, DETECTING MEANS COUPLED TO THE OUTPUT OF SAIDFIRST PULSE GENERATOR AND TO PREDETERMINED STAGES OF SAID COUNTER MEANSFOR DETECTING THE CONDITION THEREOF UPON THE OCCURRENCE OF A FINISHPULSE, WHEREBY THE CONDITION OF THE DETECTED STAGES IS RELATED TO THEPULSE REPETITION RATE OF SAID SECOND PULSE GENERATOR, AND FREQUENCYCORRECTION MEANS COUPLED TO SAID SECOND PULSE GENERATOR AND TO THEOUTPUT OF SAID CONDITION DETECTING MEANS FOR INCREASING OR DECREASINGTHE PULSE REPETITION RATE OF SAID SECOND PULSE GENERATOR IF THECONDITION OF SAID STAGES INDICATES A DEVIATION FROM SAID PREDETERMINEDPULSE REPETITION RATE.